Digital System Test And Testable Design: Using ... May 2026

The material is structured into two main parts: developing test environments and implementing testable hardware. Key Topics Covered

Gate-level faults, fault collapsing, and structural modeling in Verilog. Digital System Test and Testable Design: Using ...

The book describes on-chip decompression algorithms in Verilog, providing a realistic look at how these impact overall chip area and performance. Key Technical Coverage The material is structured into two main parts:

Random and deterministic test generation methods, plus sequential circuit test generation. Digital System Test and Testable Design: Using ...

The book by Zainalabedin Navabi (2010) is a comprehensive guide that bridges the gap between digital design and testing methodologies. Unlike traditional texts, it uses Verilog HDL to describe and simulate test hardware, making complex concepts like fault simulation and test generation more practical and less ambiguous for designers. Core Features and Methodology